GILES simulates instruction-level side channel analysis leakage without the need for anything other that a target program. Additionally it allows for fault injection attacks to be performed concurrently.
In principle it can support multiple different processors and multiple different methods of generating leakage from these. Currently the only supported simulator is the Thumb Timing Simulator, which simulates an ARM Cortex M0 processor. We supply a range of leakage models.
This project has received funding from the European Research Council (ERC) under the European Union’s Horizon 2020 research and innovation programme (grant agreement No 725042).